`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2025/03/11 16:10:34
// Design Name: 
// Module Name: ControlUnit
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


typedef enum {
    IDLE,
    LOAD_WEIGHTS,
    LOAD_INPUTS,
    COMPUTE,
    STORE_OUTPUTS
} state_t;

module control_fsm (
    input clk,
    input rst,
    input start,
    input dma_done,
    input compute_done,
    output reg [3:0] state
);

always @(posedge clk) begin
    if (rst) begin
        state <= IDLE;
    end else begin
        case(state)
            IDLE: 
                if (start) state <= LOAD_WEIGHTS;
            LOAD_WEIGHTS:
                if (dma_done) state <= LOAD_INPUTS;
            LOAD_INPUTS:
                if (dma_done) state <= COMPUTE;
            COMPUTE:
                if (compute_done) state <= STORE_OUTPUTS;
            STORE_OUTPUTS:
                if (dma_done) state <= IDLE;
        endcase
    end
end

endmodule
